In general, semiconductor devices include an electrostatic discharge (ESD) protection circuit between a pad and a core circuit to protect the core circuit. The electrostatic discharge protection circuit prevents chip failure that is likely to occur when static electricity caused by contact between an external pin of a microchip and a charged human body or machine is discharged to a core circuit or when accumulated static electricity flows to the core circuit. In fabrication of microchips, it is an essential aspect of chip design to design a circuit for protecting a microchip from ESD stress.
A device for use in the protection circuit against the ESD stress is referred to as an ESD protection device.
FIG. 1a is a graphical representation depicting fundamental conditions for an electrostatic discharge protection device, and FIG. 1b is a graphical representation depicting an optimal condition for the ESD protection device.
The ESD protection device has to prevent current flow therethrough upon application of a voltage less than or equal to an operating voltage Vop to the ESD protection device during normal operation of a microchip adopting the ESD protection device. In order to satisfy this requirement, the avalanche voltage Vav and the triggering voltage Vtr of the ESD protection device must be greater than the operating voltage of the microchip during normal operation of the microchip (Vav, Vtr>Vop).
The ESD protection device must be able to provide sufficient protection to a core circuit in the microchip when the microchip is subjected to electrostatic discharge stress. In other words, when an ESD current flows to the microchip, it must be discharged to the outside through the ESD protection device before flowing to the core circuit. To satisfy this requirement, the triggering voltage Vtr of the ESD protection device must be sufficiently lower than the core circuit breakdown voltage Vccb of the microchip under the circumstance that ESD stress is generated in the microchip (Vtr<Vccb).
Generally, an efficient ESD protection device generally exhibits a resistance snapback characteristic wherein on-state resistance of the ESD protection device is reduced after the device is triggered. Such a resistance snapback characteristic is exhibited as a voltage snapback phenomenon wherein the corresponding voltage is lowered, despite an increase in current flowing through the ESD protection device. Here, if the snapback phenomenon becomes too severe, the ESD protection device suffers a latch-up phenomenon which allows excess current to flow through the ESD protection device, thereby causing thermal breakdown of the microchip, even in the case where the microchip is normally operated. The ESD protection device must be prevented from abnormal operation resulting from the latch-up phenomenon. To satisfy this requirement, the snapback holding voltage Vh of the ESD protection device must be greater than the operating voltage of the microchip by a sufficient safety margin (Vh>Vop+ΔV). Otherwise, the triggering current Itr must be sufficiently greater than a certain value (Itr>˜100 mA).
The ESD protection device generally adopts a multi-finger structure wherein devices having a constant size are arranged in parallel to each other for efficient use of a layout area. When such a multi-finger structure is adopted, it is necessary for the respective fingers of the ESD protection device to operate uniformly. In other words, the respective fingers of the ESD protection device cooperate to discharge an injected electrostatic discharge current to the outside. To this end, other fingers must also be triggered to cooperatively discharge the ESD current before a certain finger is triggered and suffers thermal breakdown. To satisfy this requirement, the thermal breakdown voltage Vtb of the ESD protection device must be greater than or at least similar to the triggering voltage (Vtr≦Vtb) thereof.
For normal operation of a microchip, these four conditions must be satisfied. Further, when an ESD current flows to the microchip, it is necessary for the ESD protection device to start to operate as rapidly as possible at as low a voltage as possible.
On the other hand, one fundamental characteristic for semiconductor devices operating at high voltage is that the avalanche voltage must be higher than the operating voltage. To satisfy this requirement, the semiconductor device employs, as a basic element, an N-type MOSFET having a double diffused drain, that is, a double diffused drain N-type MOSFET (DDDNMOS), as shown in FIG. 2. In order to construct the DDDNMOS structure, double impurity implantation for forming a drain is performed as shown in FIG. 2. In the DDDNMOS structure, a drain activation area 111 is formed by implanting an impurity at a sufficiently high density of 1015˜1016 cm−3, and a drain drift area 112 is formed outside the drain activation area 111 by implanting an impurity at a relatively low density of about 1013 cm−3. In most cases, a source activation area 120 has the same impurity density as the drain activation area 111 since they are formed at the same time by the impurity implantation. A P-well 100 forming a channel is formed by implanting a P-type impurity at a density of about 1012 cm−3, which is lower than the drain drift area 112. Generally, the avalanche voltage tends to increase as two adjoining areas having electrically opposite polarities decrease in impurity densities. Hence, since the DDDNMOS structure enables sufficient reduction of the impurity density for the drain drift area 112 which adjoins the P-well 100, it is possible to achieve a desired high avalanche voltage.
In order to use the DDDNMOS operating at high voltage as the ESD protection device, a gate 130, a source 120 and a well-pick up 140 are bundled and grounded on a circuit, with only the drain connected to a power terminal or an individual input/output terminal, thereby forming a grounded gate DDDNMOS (GGDDDNMOS), as shown in FIG. 2. With this electrode structure, the GGDDDNMOS does not allow an electric current to flow therethrough when a voltage applied to the drain is lower than the avalanche voltage. On the other hand, when the voltage applied to the drain increases above the avalanche voltage, impact ionization occurs at an interface between the P-well and the drain drift area to create a number of carriers, so that a parasitic NPN bipolar transistor is formed, causing a large amount of electric current to flow between the drain and the source. With this electrode structure, the GGDDDNMOS does not allow an electric current to flow therethrough at a voltage less than the avalanche voltage while allowing the current to flow therethrough at a voltage more than the avalanche voltage, thereby satisfying the fundamental characteristics for use as the ESD protection device which protects a core circuit by coping with undesired stress current during electrostatic discharge. To increase ESD stress current treatment capabilities, a multi-finger GGDDDNMOS is provided by connecting several single-finger GGDDDNMOS devices in parallel to each other.
Here, when a parasitic NPN bipolar transistor (BJT) is created in the GGDDDNMOS to allow a large amount of current to start to flow therethrough, a very low resistive current path is formed to connect the drain/channel/source areas to each other along the surface of the device, causing the current to concentrate on the device surface. Such concentration of the current on the device surface causes deterioration in capability of the GGDDDNMOS to cope with ESD stress current. In particular, since the current path has very low resistance, the thermal breakdown voltage of the GGDDDNMOS becomes lower than the triggering voltage of the BJT, thereby making it difficult to realize stable multi-finger triggering. In this way, when the current path is restrictively formed along the surface of the device to cause concentration of the current only on the device surface, a surface temperature of the device sharply rises even at low current, thereby causing the thermal breakdown phenomenon on the surface of the device. As a result, the capability of the device to cope with the ESD stress current is significantly deteriorated.
FIG. 3 is a graphical representation depicting typical voltage-current characteristics of a GGDDDNMOS device operating as an ESD protection device.
In view of a design window of the ESD protection device, the GGDDDNMOS cannot be used as the ESD protection device due to the following two problems.
Firstly, the GGDDDNMOS is not sufficiently strong against ESD stress current. In other words, the GGDDDNMOS cannot cope with a large amount of electrostatic current. Secondly, the thermal breakdown voltage of the GGDDDNMOS is lower than the triggering to voltage of the BJT (Vtr≧Vtb). As a result, the respective fingers of the multi-finger structure do not operate uniformly.
Therefore, to ensure effective coping with ESD stress of a microchip operating at high voltage, there is a need for an ESD protection device that can solve the problems of the GGDDDNMOS while exhibiting high avalanche voltage characteristics.